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XC4VLX25-11SFG363I 500MHz 240 I/O IC FPGA

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XC4VLX25-11SFG363I 500MHz 240 I/O IC FPGA

Name: XC4VLX2511SFG363I 500MHz 240 IO IC FPGA
Brand: Xilinx Inc.
Price: 400 USD

Brand Name : Xilinx Inc.

Model Number : XC4VLX25-11SFG363I

Certification : Lead free / RoHS Compliant

MOQ : 1 pcs

Price : USD 400~1000 pcs

Payment Terms : T/T, Western Union, Paypal, Trade Assurance, Credit Card

Supply Ability : 382 pcs

Delivery Time : 3-5 Day

Packaging Details : International Standard Packaging

Category : Programmable Logic ICs

Condition : Original 100%,Brand New and Original,New

Number of I/Os : 240 I/O

Product : Virtex-4

Package / Case : FBGA-363

Distributed RAM : 168 kbit

Embedded Block RAM - EBR : 1296 kbit

Maximum Operating Frequency : 500 MHz

Service : BOM Kitting

Lead time : In Stock,contact us

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XC4VLX25-11SFG363I IC FPGA FBGA-363 240 I/O Virtex-4

Product Attribute	Attribute Value
Manufacturer:	Xilinx
Product Category:	FPGA - Field Programmable Gate Array
Product:	Virtex-4
Number of Logic Elements:	24192
Number of I/Os:	240 I/O
Operating Supply Voltage:	1.2 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 100 C
Mounting Style:	SMD/SMT
Package / Case:	FBGA-363
Series:	XC4VLX25
Brand:	Xilinx
Distributed RAM:	168 kbit
Embedded Block RAM - EBR:	1296 kbit
Maximum Operating Frequency:	500 MHz
Moisture Sensitive:	Yes
Product Type:	FPGA - Field Programmable Gate Array
Factory Pack Quantity:	1
Subcategory:	Programmable Logic ICs
Tradename:	Virtex
Unit Weight:	5.500445 oz

Summary of Virtex-4 FPGA Features

• Smart RAM Memory Hierarchy
- Distributed RAM
- Dual-port 18-Kbit RAM blocks
· Optional pipeline stages
· Optional programmable FIFO logic automatically remaps RAM signals as FIFO signals
- High-speed memory interface supports DDR and DDR-2 SDRAM, QDR-II, and RLDRAM-II.

• 1.2V Core Voltage

• Flip-Chip Packaging including Pb-Free Package Choices

• Programmable single-ended or differential (LVDS) operation
• Input block with an optional single data rate (SDR) or double data rate (DDR) register
• Output block with an optional SDR or DDR register
• Bidirectional block
• Per-bit deskew circuitry
• Dedicated I/O and regional clocking resources
• Built in data serializer/deserializer

The IOB registers are either edge-triggered D-type flip-flops or level-sensitive latches.
IOBs support the following single-ended standards:
• LVTTL
• LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
• PCI (33 and 66 MHz)
• PCI-X
• GTL and GTLP
• HSTL 1.5V and 1.8V (Class I, II, III, and IV)
• SSTL 1.8V and 2.5V (Class I and II)

XC4VLX25-11SFG363I 500MHz 240 I/O IC FPGA

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XC4VLX25-11SFG363I 500MHz 240 I/O IC FPGA Images

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XC4VLX25-11SFG363I 500MHz 240 I/O IC FPGA

XC4VLX25-11SFG363I 500MHz 240 I/O IC FPGA

XC4VLX25-11SFG363I

240 I/O IC FPGA

500MHz xilinx virtex 4

XC4VLX25-11SFG363I 500MHz 240 I/O IC FPGA Images