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EP3SE80F780C3N 500kbit Field Programmable Gate Array

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EP3SE80F780C3N 500kbit Field Programmable Gate Array

Brand Name : Intel / Altera

Model Number : EP3SE80F780C3N

Certification : Lead free / RoHS Compliant

MOQ : 1 pcs

Price : USD 2000-30000 pcs

Payment Terms : T/T, Western Union, Paypal, Trade Assurance, Credit Card

Supply Ability : 136pcs

Delivery Time : 3-5 Day

Packaging Details : International Standard Packaging

Category : IC FPGA

Condition : Original 100%,Brand New and Original,New

Series : Stratix III Enhanced

Number of Logic Array Blocks - LABs : 3200

Number of I/Os : 488 I/O

Package / Case : FBGA-780

Operating Supply Voltage : 1.2 V to 3.3 V

Embedded Block RAM - EBR : 500 kbit

Service : BOM Kitting

Lead time : In Stock,contact us

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EP3SE80F780C3N Field Programmable Gate Array Stratix III Enhanced

Product Attribute Attribute Value
Intel
FPGA - Field Programmable Gate Array
Stratix III Enhanced
80000
3200
488 I/O
1.2 V to 3.3 V
0 C
+ 70 C
SMD/SMT
FBGA-780
Tray
Series: Stratix III
Brand: Intel / Altera
Embedded Block RAM - EBR: 500 kbit
Moisture Sensitive: Yes
Product Type: FPGA - Field Programmable Gate Array
Factory Pack Quantity: 36
Subcategory: Programmable Logic ICs
Total Memory: 6683 kbit
Tradename: Stratix
Part # Aliases: 971852

Stratix III devices offer the following features:
■ Support for multiple intellectual property megafunctions from Altera® MegaCore® functions and Altera Megafunction Partners Program (AMPPSM)
■ Support for high-speed networking and communications bus standards including SPI-4.2, SFI-4, SGMII, Utopia IV, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI
■ The only high-density, high-performance FPGA with support for 256-bit AES volatile and non-volatile security key to protect designs
■ High-speed DSP blocks provide dedicated implementation of 9×9, 12×12, 18×18, and 36×36 multipliers (at up to 550 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters
■ I/O:GND:PWR ratio of 8:1:1 along with on-die and on-package decoupling for robust signal integrity
■ Programmable Power Technology, which minimizes power while maximizing device performance
■ Up to 12 phase-locked loops (PLLs) per device that support PLL reconfiguration, clock switchover, programmable bandwidth, clock synthesis, and dynamic phase shifting
■ Memory interface support with dedicated DQS logic on all I/O banks
■ Support for high-speed external memory interfaces including DDR, DDR2, DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular I/O banks



EP3SE80F780C3N 500kbit Field Programmable Gate Array


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